It was 2004, and three of our founders were attending an international symposium they organized on Clockless Computing (Coordinating Billions of Transistors), at Washington University in St. Louis, Missouri.  In the program, leaders in asynchronous computing reviewed future design challenges imposed on IC densities according to Moore’s Law.

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    Blended Integrated Circuit Systems (Blendics) is an approach that utilizes both traditional and new design methods to enable the continued evolution of the integrated circuit.  With Blendics’ solutions, your organization can continue to leverage your expertise and investment in existing IP-Cores and standard development tools as you design and develop the Integrated Circuits (ICs) of…

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    Blendics has the first commercially available tool-set to allow IC designers to simulate synchronizer behavior and to identify issues before fabrication.  Additionally, we have a myriad of professional services to support organizations through technical challenges inhibiting their ability to innovate and grow.

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Free Software

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MetaACE LTD is a free, node-limited version of the MetaACE metastability analysis tool. MetaACE LTD provides all of the features of MetaACE except that it is limited to evalua- ting circuits with less than 250 nodes. Experience shows that many synchronizers can be evaluated quite well by including only bulk capacitance in the extracted netlists. Meta ACE LTD allows many synchronizers to be evaluated with results typically within 5-10% of true behavior. Users can use MetaACE LTD to evaluate their designs, quickly, and use the same conguration files in the professional version of MetaACE for highly accurate simulations of fully extracted netlists.


Measuring Metastability

Measuring metastability is just 50 years old this year. In 1965 my colleague Tom Chaney took a sampling ‘scope picture of an ECL flip-flop going metastable. S. Lubkin had made mention of the phenomenon over a decade before that, but at that time most engineers were unaware of the phenomenon or did not believe it…


WEBINAR: Improving Chip Reliability Through Synchronizer Optimization

Date & Time Wednesday, February 18, 2015 1:00PM to 2:00 PM CST Register Description In this webinar a panel of experts will discuss the role of synchronizer design in modern chip development. Using traditional approaches, in both design and characterization of modern synchronizers, has resulted in reduced reliability. However, tremendous advancements have been made to…





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