It was 2004, and three of our founders were attending an international symposium they organized on Clockless Computing (Coordinating Billions of Transistors), at Washington University in St. Louis, Missouri. In the program, leaders in asynchronous computing reviewed future design challenges imposed on IC densities according to Moore’s Law.
Blended Integrated Circuit Systems (Blendics) is an approach that utilizes both traditional and new design methods to enable the continued evolution of the integrated circuit. With Blendics’ solutions, your organization can continue to leverage your expertise and investment in existing IP-Cores and standard development tools as you design and develop the Integrated Circuits (ICs) of…
Blendics has the first commercially available tool-set to allow IC designers to simulate synchronizer behavior and to identify issues before fabrication. Additionally, we have a myriad of professional services to support organizations through technical challenges inhibiting their ability to innovate and grow.
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MetaACE LTD is a free, node-limited version of the MetaACE metastability analysis tool. MetaACE LTD provides all of the features of MetaACE except that it is limited to evalua- ting circuits with less than 250 nodes. Experience shows that many synchronizers can be evaluated quite well by including only bulk capacitance in the extracted netlists. Meta ACE LTD allows many synchronizers to be evaluated with results typically within 5-10% of true behavior. Users can use MetaACE LTD to evaluate their designs, quickly, and use the same conguration files in the professional version of MetaACE for highly accurate simulations of fully extracted netlists.
– Jerry Cox The Clock-Domain-Crossing conundrum is this: Where is the evidence of Clock-Domain-Crossing (CDC) failures that have occurred during a product’s service life? We know there have been products that have had CDC failures during test and been re-spun,...read more
Steve Golson Trilobyte Systems ABSTRACT The phenomenon of metastability is inherent in clocked digital logic. Many techniques have been presented for minimizing metastability, both for crossing clock domains, and for handling asynchronous inputs. Some of these “best...read more