• ABOUT BLENDICS

    It was 2004, and three of our founders were attending an international symposium they organized on Clockless Computing (Coordinating Billions of Transistors), at Washington University in St. Louis, Missouri.  In the program, leaders in asynchronous computing reviewed future design challenges imposed on IC densities according to Moore’s Law.

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  • INNOVATION

    Blended Integrated Circuit Systems (Blendics) is an approach that utilizes both traditional and new design methods to enable the continued evolution of the integrated circuit.  With Blendics’ solutions, your organization can continue to leverage your expertise and investment in existing IP-Cores and standard development tools as you design and develop the Integrated Circuits (ICs) of…

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  • SOLUTIONS

    Blendics has the first commercially available tool-set to allow IC designers to simulate synchronizer behavior and to identify issues before fabrication.  Additionally, we have a myriad of professional services to support organizations through technical challenges inhibiting their ability to innovate and grow.

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Free Software

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MetaACE LTD is a free, node-limited version of the MetaACE metastability analysis tool. MetaACE LTD provides all of the features of MetaACE except that it is limited to evalua- ting circuits with less than 250 nodes. Experience shows that many synchronizers can be evaluated quite well by including only bulk capacitance in the extracted netlists. Meta ACE LTD allows many synchronizers to be evaluated with results typically within 5-10% of true behavior. Users can use MetaACE LTD to evaluate their designs, quickly, and use the same conguration files in the professional version of MetaACE for highly accurate simulations of fully extracted netlists.

NEWS

Simulating the Behavior of Synchronizers

J. Cox, T. Chaney, D. Zar 13 Feb 2011 By simulating the behavior of a synchronizer, an estimate of its Mean-Time-Between-Failures (MTBF) can be obtained. The method for estimating MTBF described here was originally based on the work of Molnar and Rosenberger [1], work which depended heavily for its success on their extensive experience in…

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Beware of Parameter Variability in Clock Domain Crossings

How should we assess the risk of harmful metastability in a clock domain crossing (CDC) when the semiconductor process has significant parameter variability? One possibility is to determine the MTBF of a synchronizer at the worst-case corner of the CDC. But that approach has some conflicting complications: Synchronizer failures can occur at any time before…

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