Improving Computer Scalability & Reliability to Enable Continued Technology Advancement

On November 16, 2011, the National Science Foundation awarded an SBIR (Small Business Innovation Research) Phase I grant to Blendics.

This grant supported Blendics’ development of a wrapper technology. This technology makes each SoC subsystem appear as if it were clock-free (asynchronous) and independent of its neighbors, thereby reducing the undesirable effects of transistor variability and enabling power reduction techniques. The goal of the research is to automate this design task, making widespread use of these wrappers more economical.

The company’s approach blends clock-free and clocked design paradigms thereby retaining the advantages of conventional tools while avoiding their disadvantages. The intended project outcomes are:

  • The design of a family of Delay-tolerant, Asynchronous Interfaces (DANI), which can be assembled into a wrapper for traditionally designed, clocked-components
  • Creation of an automatic wrapper generator that will allow the wrapped components to appear to their neighbors as if they were clock-free
  • Validation that the wrapper generator functions properly on a set of components randomly chosen from a popular silicon-IP website.

This is a critical step iin the creation of a new class of SoC design tools that fit well with existing tools, but make possible relative timing between components instead of the current, but fragile synchronous timing between components. By adopting this new class of SoC design tools, the IC designer saves significant design time and overall project cost.