On June 26, 2012, Blendics was awarded $499,862 in supplemental Phase IIB funding from the National Science Foundation. This follows prior funding through NSF’s Small Business Technology Transfer program. This grant will support continued research and testing of the Blendics tools. These tools support multi-synchronous design techniques that create an asynchronous network-on-chip (ANoC).
The benefits of this approach are:
- Reduced time-to-market. By eliminating costly design iterations often needed to achieve timing closure, Blendics tools dramatically reduce time-to-market.
- Reduced power and increased reliability. The integration of a product into an SoC can substantially reduce power requirements by eliminating many off-chip signal paths and by stopping clocks in idle subsystems. Furthermore, a product with fewer parts has fewer ways to fail.
- Reduced NRE costs. The minimization of engineering time and the reuse of IP cores make possible the integration of products that would not ordinarily fit within the budget constraints associated with low production.
The bottom line is that a reduction in engineering time by up to half is possible with the Blendics flow