Improving Computer Scalability & Reliability to Enable Continued Technology Advancement

Synchronization and Metastability

Steve Golson Trilobyte Systems ABSTRACT The phenomenon of metastability is inherent in clocked digital logic. Many techniques have been presented for minimizing metastability, both for crossing clock domains, and for handling asynchronous inputs. Some of these “best...

Ambiguous Behavior of Logic Bistable Systems

Marco Hurtado and David Elliott Washington University, St. Louis First presented at Allerton Conference, October 1-4, 1975 ABSTRACT The standard specifications of logic bistable devices do not specify the behavior under conditions in which the input is logically...

Simulating the Behavior of Synchronizers

J. Cox, T. Chaney, D. Zar 13 Feb 2011 By simulating the behavior of a synchronizer, an estimate of its Mean-Time-Between-Failures (MTBF) can be obtained. The method for estimating MTBF described here was originally based on the work of Molnar and Rosenberger [1], work...

Transistor Variability and Synchronizer Failures

Jerry Cox, ScD Two new tools, MetaACE and PublicSync, have been recently introduced by Blendics. Together they are capable of the analysis of many aspects of synchronizer performance. The benchmark circuit, PublicSync, can be simulated by the analysis tool, MetaACE,...

Webinar Recording: Improving Chip Reliability…

Click the link below to view the full recording of our recent webinar:  Improving Chip Reliability Through Synchronizer Optimization VIEW FULL RECORDING In this webinar a panel of experts will discuss the role of synchronizer design in modern chip development. Using...

Real World Examples of Metastability

Jerry Cox From the beginning, now some 50 years ago, we often ran into requests for help such as: “we need help, but this work needs to confidential. If this became known, it would damage the reputation of our product.” It was, and is, rare where we were allowed to...