In a perfect world of chip design, there would be no margin of error. However, as many engineers and only a few programmers know, digital signals do not instantly change from 0 to 1 or vice versa. It may take less than a nanosecond, but all the values of voltage in between the two valid ones representing 1 and 0 must be traversed during these transitions.
The circuit designer, aided by his or her EDA tool flow, strives to avoid catching a signal in between. Nothing good can ever come from having the next circuit say, “Perhaps it was a 1 or perhaps a 0.” This perhaps condition usually arises from a fundamental an unavoidable phenomenon called metastability. Unfortunately, guarding against perhaps is getting both harder and also more important.
Reducing the risk of perhaps is getting harder because of Moore’s Law scaling (the empirical observation that the number of transistors that can be fit on a fixed chip area doubles about every two years.) More transistors on a chip mean more power consumption.