Improving Computer Scalability & Reliability to Enable Continued Technology Advancement



Consider the IC designer’s paradox. Simultaneously, he or she must deliver increased processing complexity, greater speed and manage power consumption. Did we mention it all must work reliably and with consistency? These challenges are monumental.

So, how to make a higher performing, more reliable mousetrap? At Blendics, we considered the problem long and hard, from both a scientific and engineering perspective and had an idea…We believe the answer lies in optimizing the communications between the integrated circuit’s component parts.

To be more specific, within each IC’s design there are defined communication pathways between the components, including: point-to-point, one-to-many and many-to-one connections, some unidirectional and some bi-directional paths. In current designs, these communication paths are synchronized by a global clock tree, a structure which has extremely stringent timing requirements and is increasingly difficult to manage. Add to that, the clock tree takes up increasing amounts of space and consumes more and more power.

As communication speed increases and the paths between components get longer, it becomes physically impossible to meet the stringent timing requirements imposed by the clock without adding pipeline stages. However, when these timing buffers are added a number of unwanted effects are introduced including: increased latency, decreased performance, increased power consumption and an increased overall design complexity.

If that wasn’t enough, many of the components operate at different speeds which increases the complexity, splitting it into multiple clock domains, each requiring one or more clock domain crossings. The heart of a clock domain crossing is a synchronizer, used to make sure data accurately flows from one clock domain to another. To satisfy power constraints in these synchronizers the distinction between a 0 and a 1 has become so small, it is increasingly difficult to reliably determine which state a synchronizer is in. This makes it more difficult for synchronizers to do their job resulting in increasing risk of failure due to metastability. Bottom line, it can be a mess.

Ultimately, the problem boils down to reliable communication between components, often referred to as timing closure


Blendics looked at the Designer’s challenges and while it’s clear that they are able to effectively reuse or create new IP-Cores providing the additional functionality demanded for next generation devices. It is also evident that IC fabricators are able to effectively develop next generation techniques, creating the ability to add more and more logic to a single IC. However, the problem is that when designers connect all of the components together, they are too often unable to achieve reliable communication at the required speeds.

The Logical Question

Then we asked the question, “If each component is really an independent entity, why are Designers still trying to use traditional synchronous techniques to make them all act as though they are operating in complete unison?”

Our Answer

Eliminate the global clock tree, and in its place provide a new communication path for each component. This new approach allows each component to operate independently, and at its optimal design speed; thus achieving scalability and reliability.


Tom Chaney, one of the Blendics founders, was first to document the metastability phenomenon and, over the years, has been an important contributor to many publications in scientific journals on the subject. Blendics along with colleagues in Israel have published verification of the accuracy of our MetaACE tool by comparing it with measurements in silicon taken across wide variations in process, supply voltage and temperature.


Synchronizer failure in modern safety critical IC’s can lead to extreme consequences. These failures occur randomly and leave no evidence as to the cause of the problem. In addition, many times safety critical IC’s are subjected to extreme conditions such as high heat, extreme cold or fluctuations in power which can expose the IC to operating regions which raise the chances of synchronizer failure (MTBF). MetaACE analyzes synchronizers to verify that their reliability is adequate for the application regardless of the process used to create it or the temperature and voltage at which the IC is being operated. As demand increases for safety-critical SoC devices, such as those required for the cars of the future, the level of reliability required will increase by several orders of magnitude. MetaACE fills the emerging need for verification of synchronizer reliability.


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