Improving Computer Scalability & Reliability to Enable Continued Technology Advancement

Date & Time
Wednesday, February 18, 2015
1:00PM to 2:00 PM CST


In this webinar a panel of experts will discuss the role of synchronizer design in modern chip development. Using traditional approaches, in both design and characterization of modern synchronizers, has resulted in reduced reliability. However, tremendous advancements have been made to improve synchronizers through proper characterization by utilizing a newly available tool, MetaACE, that simulates synchronizer behavior. By leveraging automated tools, the design and development of robust synchronizers is simple, fast and results in superior reliability.

Who Should Attend?
Anyone involved with integrated circuit design, such as cell designers, SoC developers, verification engineers

1 – Panel Introductions
2 – Characterizing Synchronizers in Clock Domain Crossings and other surprising places
3 – Synchronizer Reliability
4 – Using Automated Simulation to Improve Synchronizer Reliability
5 – Demo: Automated Simulation of a publicly available synchronizer
6 – Q & A

Keynote Speaker
Salomon (Shlomi) Beer
Shlomi Beer received the B.Sc in computer engineering (Summa Cum Laude) and B.A in Physics (Summa Cum Laude) in 2004 and Ph.D. degree in computer engineering in 2014 from the Technion— Israel Institute of Technology, where he was a Haso-Plattner-institut (HPI) fellow. His doctoral research broke new ground in metastability analysis and measurement and these results have been reported in nice specific scientific publications.

During 2005 to 2011 he held engineering and algorithmic positions in Freescale Semiconductor. In 2014 he joined the Priceline group where he manages the data science and algorithmic division in the Israel research center. He authored several publications and patents in the field of computer architecture, VLSI systems, computer vision algorithms, bidding systems, statistical modeling and machine learning.