Click the link below to view the full recording of our recent webinar: Improving Chip Reliability Through Synchronizer Optimization
In this webinar a panel of experts will discuss the role of synchronizer design in modern chip development. Using traditional approaches, in both design and characterization of modern synchronizers, has resulted in reduced reliability. However, tremendous advancements have been made to improve synchronizers through proper characterization by utilizing a newly available tool, MetaACE, that simulates synchronizer behavior. By leveraging automated tools, the design and development of robust synchronizers is simple, fast and results in superior reliability.